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36-Mbit QDR II SRAM 4-Word Burst Architecture
36-Mbit QDR(R) II SRAM 4-Word Burst Architecture
CY7C1411KV18, CY7C1426KV18 CY7C1413KV18, CY7C1415KV18 (R)
Features
Configurations
CY7C1411KV18 - 4 M x 8 CY7C1426KV18 - 4 M x 9 CY7C1413KV18 - 2 M x 18 CY7C1415KV18 - 1 M x 36
Separate independent read and write data ports Supports concurrent transactions 333 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double data rate (DDR) Interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz Two input clocks (K and K) for precise DDR timing SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches Echo clocks (CQ and CQ) simplify data capture in high speed systems Single multiplexed address input bus latches address inputs for read and write ports Separate port selects for depth expansion Synchronous internally self-timed writes QDR(R) II operates with 1.5 cycle read latency when DOFF is asserted HIGH Operates similar to QDR I device with 1 cycle read latency when DOFF is asserted LOW Available in x 8, x 9, x 18, and x 36 configurations Full data coherency, providing most current data Core VDD = 1.8 V (0.1 V); I/O VDDQ = 1.4 V to VDD Supports both 1.5 V and 1.8 V I/O supply Available in 165-ball FBGA package (13 x 15 x 1.4 mm) Offered in both Pb-free and non Pb-free Packages Variable drive HSTL output buffers JTAG 1149.1 compatible test access port Phase locked loop (PLL) for accurate data placement

Functional Description
The CY7C1411KV18, CY7C1426KV18, CY7C1413KV18, and CY7C1415KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to "turnaround" the data bus that exists with common I/O devices. Each port can be accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR II read and write ports are independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 8-bit words (CY7C1411KV18), 9-bit words (CY7C1426KV18), 18-bit words (CY7C1413KV18), or 36-bit words (CY7C1415KV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus `turnarounds'. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Selection Guide
Description Maximum operating frequency Maximum operating current x8 x9 x 18 x 36 333 MHz 333 560 560 570 790 300 MHz 300 520 520 540 730 250 MHz 250 460 460 470 640 200 MHz 200 400 400 410 540 167 MHz 167 360 360 370 480 Unit MHz mA
Cypress Semiconductor Corporation Document Number: 001-57826 Rev. *B
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised March 1, 2011
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CY7C1411KV18, CY7C1426KV18 CY7C1413KV18, CY7C1415KV18
Logic Block Diagram (CY7C1411KV18)
D[7:0]
8
Read Add. Decode
Write Add. Decode
A(19:0)
20
Write Reg
Address Register
Write Reg
Write Reg
Write Reg
Address Register
20
A(19:0)
1M x 8 Array
1M x 8 Array
1M x 8 Array
1M x 8 Array
K K CLK Gen.
Control Logic
RPS C C CQ
DOFF
Read Data Reg. 32
VREF WPS NWS[1:0]
16 Control Logic 16
Reg. Reg.
Reg. 8 8 8 8
CQ 8 Q[7:0]
Logic Block Diagram (CY7C1426KV18)
D[8:0]
9
Read Add. Decode
Write Add. Decode
A(19:0)
20
Write Reg
Address Register
Write Reg
Write Reg
Write Reg
Address Register
20
A(19:0)
1M x 9 Array
1M x 9 Array
1M x 9 Array
1M x 9 Array
K K CLK Gen.
Control Logic
RPS C C CQ
DOFF
Read Data Reg. 36
VREF WPS BWS[0]
18 Control Logic 18
Reg. Reg.
Reg. 9 9 9 9
CQ 9 Q[8:0]
Document Number: 001-57826 Rev. *B
Page 2 of 33
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CY7C1411KV18, CY7C1426KV18 CY7C1413KV18, CY7C1415KV18
Logic Block Diagram (CY7C1413KV18)
D[17:0]
18
Read Add. Decode
Write Add. Decode
A(18:0)
19
Write Reg
Address Register
Write Reg
Write Reg
Write Reg
Address Register
19
A(18:0)
512K x 18 Array
512K x 18 Array
512K x 18 Array
512K x 18 Array
K K CLK Gen.
Control Logic
RPS C C CQ
DOFF
Read Data Reg. 72
VREF WPS BWS[1:0]
36 Control Logic 36
Reg. Reg.
Reg. 18 18 18 18
CQ 18 Q[17:0]
Logic Block Diagram (CY7C1415KV18)
D[35:0]
36
Read Add. Decode
Write Add. Decode
A(17:0)
18
Write Reg
Address Register
Write Reg
Write Reg
Write Reg
Address Register
18
A(17:0)
256K x 36 Array
256K x 36 Array
256K x 36 Array
256K x 36 Array
K K CLK Gen.
Control Logic
RPS C C CQ
DOFF
Read Data Reg. 144
VREF WPS BWS[3:0]
72 Control Logic 72
Reg. Reg.
Reg. 36 36 36 36
CQ 36 Q[35:0]
Document Number: 001-57826 Rev. *B
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CY7C1411KV18, CY7C1426KV18 CY7C1413KV18, CY7C1415KV18
Contents
Pin Configuration ............................................................. 5 165-ball FBGA (13 x 15 x 1.4 mm) pinout .................. 5 Pin Definitions .................................................................. 7 Functional Overview ........................................................ 9 Read Operations ......................................................... 9 Write Operations ......................................................... 9 Byte Write Operations ................................................. 9 Single Clock Mode ...................................................... 9 Concurrent Transactions ........................................... 10 Depth Expansion ....................................................... 10 Programmable Impedance ........................................ 10 Echo Clocks .............................................................. 10 PLL ............................................................................ 10 Application Example ...................................................... 11 Truth Table ...................................................................... 11 Write Cycle Descriptions ............................................... 12 Write Cycle Descriptions ............................................... 12 Write Cycle Descriptions ............................................... 13 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 14 Disabling the JTAG Feature ...................................... 14 Test Access Port--Test Clock ................................... 14 Test Mode Select (TMS) ........................................... 14 Test Data-In (TDI) ..................................................... 14 Test Data-Out (TDO) ................................................. 14 Performing a TAP Reset ........................................... 14 TAP Registers ........................................................... 14 TAP Instruction Set ................................................... 14 TAP Controller State Diagram ....................................... 16 TAP Controller Block Diagram ...................................... 17 TAP Electrical Characteristics ...................................... 17 TAP AC Switching Characteristics ............................... 18 TAP Timing and Test Conditions .................................. 18 Identification Register Definitions ................................ 19 Scan Register Sizes ....................................................... 19 Instruction Codes ........................................................... 19 Boundary Scan Order .................................................... 20 Power Up Sequence in QDR II SRAM ........................... 21 Power Up Sequence ................................................. 21 PLL Constraints ......................................................... 21 Maximum Ratings ........................................................... 22 Operating Range ............................................................. 22 Neutron Soft Error Immunity ......................................... 22 Electrical Characteristics ............................................... 22 DC Electrical Characteristics ..................................... 22 AC Electrical Characteristics ..................................... 24 Capacitance .................................................................... 25 Thermal Resistance ........................................................ 25 Switching Characteristics .............................................. 26 Switching Waveforms .................................................... 28 Ordering Information ...................................................... 29 Ordering Code Definitions ......................................... 29 Package Diagram ............................................................ 30 Acronyms ........................................................................ 31 Document Conventions ................................................. 31 Units of Measure ....................................................... 31 Document History Page ................................................. 32 Sales, Solutions, and Legal Information ...................... 33 Worldwide Sales and Design Support ....................... 33 Products .................................................................... 33 PSoC Solutions ......................................................... 33
Document Number: 001-57826 Rev. *B
Page 4 of 33
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CY7C1411KV18, CY7C1426KV18 CY7C1413KV18, CY7C1415KV18
Pin Configuration
The pin configurations for CY7C1411KV18, CY7C1426KV18, CY7C1413KV18, and CY7C1415KV18 follow.[1]
165-ball FBGA (13 x 15 x 1.4 mm) pinout
CY7C1411KV18 (4 M x 8) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK 3 A NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NWS1 NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC/144M NWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS 11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI
CY7C1426KV18 (4 M x 9) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M NC NC D5 NC NC D6 VREF NC NC Q7 NC D8 NC TCK 3 A NC NC NC Q5 NC Q6 VDDQ NC NC D7 NC NC Q8 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NC NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC/144M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC NC NC D3 NC NC VREF Q2 NC NC NC NC D0 TMS 11 CQ Q4 D4 NC Q3 NC NC ZQ D2 NC Q1 D1 NC Q0 TDI
Note 1. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-57826 Rev. *B
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CY7C1411KV18, CY7C1426KV18 CY7C1413KV18, CY7C1415KV18
Pin Configuration
(continued)
The pin configurations for CY7C1411KV18, CY7C1426KV18, CY7C1413KV18, and CY7C1415KV18 follow.[1]
165-ball FBGA (13 x 15 x 1.4 mm) pinout
CY7C1413KV18 (2 M x 18) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/144M Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 A D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC/288M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC/72M NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
CY7C1415KV18 (1 M x 36) 1 A B C D E F G H J K L M N P R CQ Q27 D27 D28 Q29 Q30 D30 DOFF D31 Q32 Q33 D33 D34 Q35 TDO 2 Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK 3 D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS2 BWS3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 BWS1 BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 A 10 NC/144M Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI NC/288M NC/72M
Document Number: 001-57826 Rev. *B
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CY7C1411KV18, CY7C1426KV18 CY7C1413KV18, CY7C1415KV18
Pin Definitions
Pin Name D[x:0] I/O Pin Description InputData input signals. Sampled on the rising edge of K and K clocks when valid write operations are active. synchronous CY7C1411KV18 D[7:0] CY7C1426KV18 D[8:0] CY7C1413KV18 D[17:0] CY7C1415KV18 D[35:0] InputWrite port select active LOW. Sampled on the rising edge of the K clock. When asserted active, a synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0]. InputNibble write select 0, 1 active LOW (CY7C1411KV18 only). Sampled on the rising edge of the K and synchronous K clocks when write operations are active. Used to select which nibble is written into the device during the current portion of the write operations. NWS0 controls D[3:0] and NWS1 controls D[7:4]. All the nibble write selects are sampled on the same edge as the data. Deselecting a nibble write select ignores the corresponding nibble of data and it is not written into the device. InputByte write select 0, 1, 2, and 3 active LOW. Sampled on the rising edge of the K and K clocks when synchronous write operations are active. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1426KV18 BWS0 controls D[8:0] CY7C1413KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1415KV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the byte write selects are sampled on the same edge as the data. Deselecting a byte write select ignores the corresponding byte of data and it is not written into the device. InputAddress inputs. Sampled on the rising edge of the K clock during active read and write operations. These synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as 4 M x 8 (4 arrays each of 1 M x 8) for CY7C1411KV18, 4 M x 9 (4 arrays each of 1 M x 9) for CY7C1426KV18, 2 M x 18 (4 arrays each of 512 K x 18) for CY7C1413KV18 and 1 M x 36 (4 arrays each of 256 K x 36) for CY7C1415KV18. Therefore, only 20 address inputs are needed to access the entire memory array of CY7C1411KV18 and CY7C1426KV18, 19 address inputs for CY7C1413KV18 and 18 address inputs for CY7C1415KV18. These inputs are ignored when the appropriate port is deselected. OutputsData output signals. These pins drive out the requested data when the read operation is active. Valid synchronous data is driven out on the rising edge of the C and C clocks during read operations, or K and K when in single clock mode. On deselecting the read port, Q[x:0] are automatically tristated. CY7C1411KV18 Q[7:0] CY7C1426KV18 Q[8:0] CY7C1413KV18 Q[17:0] CY7C1415KV18 Q[35:0] InputRead port select active LOW. Sampled on the rising edge of positive input clock (K). When active, a synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is allowed to complete and the output drivers are automatically tristated following the next rising edge of the C clock. Each read access consists of a burst of four sequential transfers. Input clock Positive input clock for output data. C is used in conjunction with C to clock out the read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 11 for further details. Negative input clock for output data. C is used in conjunction with C to clock out the read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 11 for further details. Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative input clock input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode.
WPS NWS0, NWS1,
BWS0, BWS1, BWS2, BWS3
A
Q[x:0]
RPS
C
C
Input clock
K K
Input clock Input clock
Document Number: 001-57826 Rev. *B
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CY7C1411KV18, CY7C1426KV18 CY7C1413KV18, CY7C1415KV18
Pin Definitions
Pin Name CQ I/O Echo clock
(continued) Pin Description CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the Switching Characteristics on page 26. CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the Switching Characteristics on page 26. Output impedance matching input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. PLL turn off active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin is connected to a pull up through a 10 K or less pull-up resistor. The device behaves in QDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with QDR I timing. TDO for JTAG. TCK pin for JTAG. TDI pin for JTAG. TMS pin for JTAG. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points. Ground for the device.
CQ
Echo clock
ZQ
Input
DOFF
Input
TDO TCK TDI TMS NC
Output Input Input Input N/A N/A N/A N/A Inputreference Ground
NC/72M NC/144M NC/288M
VREF VDD VSS VDDQ
Power supply Power supply inputs to the core of the device. Power supply Power supply inputs for the outputs of the device.
Document Number: 001-57826 Rev. *B
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CY7C1411KV18, CY7C1426KV18 CY7C1413KV18, CY7C1415KV18
Functional Overview
The CY7C1411KV18, CY7C1426KV18, CY7C1413KV18, CY7C1415KV18 are synchronous pipelined burst SRAMs with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and flows out through the read port. These devices multiplex the address inputs to minimize the number of address pins required. By having separate read and write ports, the QDR II completely eliminates the need to turn around the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of four 8-bit data transfers in the case of CY7C1411KV18, four 9-bit data transfers in the case of CY7C1426KV18, four 18-bit data transfers in the case of CY7C1413KV18, and four 36-bit data transfers in the case of CY7C1415KV18 in two clock cycles. This device operates with a read latency of one and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to VSS then device behaves in QDR I mode with a read latency of one clock cycle. Accesses for both ports are initiated on the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the output clocks (C and C, or K and K when in single clock mode). All synchronous data inputs (D[x:0]) pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the output clocks (C and C, or K and K when in single clock mode). All synchronous control (RPS, WPS, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K and K). CY7C1413KV18 is described in the following sections. The same basic descriptions apply to CY7C1411KV18, CY7C1426KV18 and CY7C1415KV18. the device ignores the second read request. Read accesses can be initiated on every other K clock rise. Doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the output clocks (C and C, or K and K when in single clock mode). When the read port is deselected, the CY7C1413KV18 first completes the pending read transactions. Synchronous internal circuitry automatically tristates the outputs following the next rising edge of the positive output clock (C). This enables a seamless transition between devices without the insertion of wait states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the following K clock rise the data presented to D[17:0] is latched and stored into the lower 18-bit write data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock (K) the information presented to D[17:0] is also stored into the write data register, provided BWS[1:0] are both asserted active. This process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, write accesses to the device cannot be initiated on two consecutive K clock rises. The internal logic of the device ignores the second write request. Write accesses can be initiated on every other rising edge of the positive input clock (K). Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K). When deselected, the write port ignores all inputs after the pending write operations are completed.
Byte Write Operations
Byte write operations are supported by the CY7C1413KV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate byte write select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the byte write select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature is used to simplify read, modify, or write operations to a byte write operation.
Read Operations
The CY7C1413KV18 is organized internally as four arrays of 512 K x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the positive input clock (K). The address presented to the address inputs is stored in the read address register. Following the next K clock rise, the corresponding lowest order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C, the next 18-bit data word is driven onto the Q[17:0]. This process continues until all four 18-bit data words are driven out onto Q[17:0]. The requested data is valid 0.45 ns from the rising edge of the output clock (C or C, or K or K when in single clock mode). To maintain the internal logic, each read access must be enabled to complete. Each read access consists of four 18-bit data words and takes two clock cycles to complete. Therefore, read accesses to the device cannot be initiated on two consecutive K clock rises. The internal logic of
Single Clock Mode
The CY7C1411KV18 is used with a single clock that controls both the input and output registers. In this mode the device recognizes only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power on. This function is a strap option and not alterable during device operation.
Document Number: 001-57826 Rev. *B
Page 9 of 33
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CY7C1411KV18, CY7C1426KV18 CY7C1413KV18, CY7C1415KV18
Concurrent Transactions
The read and write ports on the CY7C1413KV18 operate independently of one another. As each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port. If the ports access the same location when a read follows a write in successive clock cycles, the SRAM delivers the most recent information associated with the specified address location. This includes forwarding data from a write cycle that was initiated on the previous K clock rise. Read access and write access must be scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports are deselected, the read port takes priority. If a read was initiated on the previous cycle, the write port takes priority (as read operations cannot be initiated on consecutive cycles). If a write was initiated on the previous cycle, the read port takes priority (as write operations cannot be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state results in alternating read or write operations being initiated, with the first access being a read. range of RQ to guarantee impedance matching with a tolerance of 15% is between 175 and 350 , with VDDQ = 1.5 V. The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR II to simplify data capture on high speed systems. Two echo clocks are generated by the QDR II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free running clocks and are synchronized to the output clock of the QDR II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timing for the echo clocks is shown in the Switching Characteristics on page 26.
PLL
These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the PLL is locked after 20 s of stable clock. The PLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary to reset the PLL to lock to the desired frequency. The PLL automatically locks 20 s after a stable clock is presented. The PLL may be disabled by applying ground to the DOFF pin. When the PLL is turned off, the device behaves in QDR I mode (with one cycle latency and a longer access time).
Depth Expansion
The CY7C1413KV18 has a port select input for each port. This enables for easy depth expansion. Both port selects are sampled on the rising edge of the positive input clock only (K). Each port select input can deselect the specified port. Deselecting a port does not affect the other port. All pending transactions (read and write) are completed before the device is deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5 x the value of the intended line impedance driven by the SRAM, the allowable
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Application Example
Figure 1 shows four QDR II used in an application. Figure 1. Application Example
SRAM #1
Vt R D A R P S # W P S # B W S #
ZQ CQ/CQ# Q C C# K K#
R = 250ohms R P S # W P S #
SRAM #4
D A B W S #
ZQ R = 250ohms CQ/CQ# Q C C# K K#
DATA IN DATA OUT Address RPS# BUS WPS# MASTER BWS# (CPU CLKIN/CLKIN# or Source K ASIC) Source K# Delayed K Delayed K# R R = 50ohms Vt = Vddq/2
R
Vt Vt
Truth Table
The truth table for CY7C1411KV18, CY7C1426KV18, CY7C1413KV18, and CY7C1415KV18 follows.[2, 3, 4, 5, 6, 7] Operation Write cycle: Load address on the rising edge of K; input write data on two consecutive K and K rising edges. Read cycle: Load address on the rising edge of K; wait one and a half cycle; read data on two consecutive C and C rising edges. NOP: No operation Standby: Clock stopped K L-H RPS WPS H[8] L[9] DQ DQ DQ DQ D(A) at K(t + 1) D(A + 1) at K(t + 1) D(A + 2) at K(t + 2) D(A + 3) at K(t + 2)
L-H
L[9]
X
Q(A) at C(t + 1) Q(A + 1) at C(t + 2) Q(A + 2) at C(t + 2) Q(A + 3) at C(t + 3)
L-H Stopped
H X
H X
D=X Q = High Z Previous state
D=X Q = High Z Previous state
D=X Q = High Z Previous state
D=X Q = High Z Previous state
Notes 2. X = "Don't Care," H = Logic HIGH, L = Logic LOW, represents rising edge. 3. Device powers up deselected with the outputs in a tristate condition. 4. "A" represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst. 5. "t" represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the "t" clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. If this signal was LOW to initiate the previous cycle, this signal becomes a "Don't Care" for this operation. 9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the second read or write request.
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Write Cycle Descriptions
The write cycle description table for CY7C1411KV18 and CY7C1413KV18 follows.[10, 11] BWS0/ BWS1/ NWS0 L NWS1 L K L-H K - Comments During the data portion of a write sequence CY7C1411KV18 both nibbles (D[7:0]) are written into the device. CY7C1413KV18 both bytes (D[17:0]) are written into the device.
L
L
-
L-H During the data portion of a write sequence CY7C1411KV18 both nibbles (D[7:0]) are written into the device. CY7C1413KV18 both bytes (D[17:0]) are written into the device. - During the data portion of a write sequence CY7C1411KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C1413KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
H
L-H
L
H
-
L-H During the data portion of a write sequence CY7C1411KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C1413KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. - During the data portion of a write sequence CY7C1411KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C1413KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
L
L-H
H
L
-
L-H During the data portion of a write sequence CY7C1411KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C1413KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. - No data is written into the devices during this portion of a write operation. L-H No data is written into the devices during this portion of a write operation.
H H
H H
L-H -
Write Cycle Descriptions
The write cycle description table for CY7C1426KV18 follows. [10, 11] BWS0 L L H H K L-H - L-H - K - L-H - L-H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. No data is written into the device during this portion of a write operation. No data is written into the device during this portion of a write operation.
Notes 10. X = "Don't Care," H = Logic HIGH, L = Logic LOW, represents rising edge. 11. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved.
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Write Cycle Descriptions
BWS0 L L L L H H H H H H H H BWS1 L L H H L L H H H H H H BWS2 L L H H H H L L H H H H BWS3 L L H H H H H H L L H H
The write cycle description table for CY7C1415KV18 follows.[12, 13] K L-H - L-H - L-H - L-H - L-H - L-H - K - Comments During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device.
L-H During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. - During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered.
L-H During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. - During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered.
L-H During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. - During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered.
L-H During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. - During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered.
L-H During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. - No data is written into the device during this portion of a write operation. L-H No data is written into the device during this portion of a write operation.
Notes 12. X = "Don't Care," H = Logic HIGH, L = Logic LOW, represents rising edge. 13. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved.
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IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8 V I/O logic levels. Instruction Register Three-bit instructions are serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in TAP Controller Block Diagram on page 17. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that is placed between TDI and TDO pins. This enables shifting of data through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several No Connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions are used to capture the contents of the input and output ring. The Boundary Scan Order on page 20 shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 19.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull up resistor. TDO must be left unconnected. Upon power-up, the device comes up in a reset state, which does not interfere with the operation of the device.
Test Access Port--Test Clock
The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP Controller State Diagram on page 16. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the registers. The output is active, depending upon the current state of the TAP state machine (see Instruction Codes on page 19). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This Reset does not affect the operation of the SRAM and can be performed when the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a high Z state.
TAP Instruction Set
Eight different instructions are possible with the three-bit instruction register. All combinations are listed in Instruction Codes on page 19. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in this section in detail. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK.
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IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test-Logic-Reset state. SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a high Z state until the next command is supplied during the Update IR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured in the boundary scan register. The TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift-DR controller state. EXTEST OUTPUT BUS TRISTATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tristate mode. The boundary scan register has a special bit located at bit #108. When this scan cell, called the "extest output bus tristate," is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a high Z condition. This bit is set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
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TAP Controller State Diagram
The state diagram for the TAP controller follows.[14]
1
TEST-LOGIC RESET 0 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 1 0 0 1 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 0 0 1 0
0
TEST-LOGIC/ IDLE
1
SELECT DR-SCAN 0 1
1
Note 14. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
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TAP Controller Block Diagram
0 Bypass Register 2 TDI Selection Circuitry 31 Instruction Register 30 29 . . 2 1 0 1 0 Selection Circuitry TDO
Identification Register 108 . . . . 2 1 0
Boundary Scan Register
TCK TMS TAP Controller
TAP Electrical Characteristics
Over the Operating Range[15, 16, 17] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH voltage Output HIGH voltage Output LOW voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input and output load current GND VI VDD Test Conditions IOH =2.0 mA IOH =100 A IOL = 2.0 mA IOL = 100 A Min 1.4 1.6 - - Max - - 0.4 0.2 Unit V V V V V V A
0.65VDD VDD + 0.3 -0.3 -5 0.35VDD 5
Notes 15. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table. 16. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5 V (Pulse width less than tCYC/2). 17. All voltage referenced to Ground.
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TAP AC Switching Characteristics
Over the Operating Range[18, 19] Parameter tTCYC tTF tTH tTL Setup Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH Output Times tTDOV tTDOX TCK clock LOW to TDO valid TCK clock LOW to TDO invalid - 0 10 - ns ns TMS hold after TCK clock rise TDI hold after clock rise Capture hold after clock rise 5 5 5 - - - ns ns ns TMS set-up to TCK clock rise TDI set-up to TCK clock rise Capture set-up to TCK rise 5 5 5 - - - ns ns ns TCK clock cycle time TCK clock frequency TCK clock HIGH TCK clock LOW Description Min 50 - 20 20 Max - 20 - - Unit ns MHz ns ns
TAP Timing and Test Conditions
Figure 2 shows the TAP timing and test conditions.[19] Figure 2. TAP Timing and Test Conditions
0.9V 50 TDO Z0 = 50 CL = 20 pF
ALL INPUT PULSES 1.8V 0.9V 0V
(a)
GND
tTH
tTL
Test Clock TCK
tTMSS tTMSH
tTCYC
Test Mode Select TMS
tTDIS tTDIH
Test Data In TDI
Test Data Out TDO
tTDOV tTDOX
Notes 18. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 19. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
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Identification Register Definitions
Instruction Field Revision number (31:29) Cypress device ID (28:12) Cypress JEDEC ID (11:1) ID register presence (0) Value CY7C1411KV18 000 CY7C1426KV18 000 CY7C1413KV18 000 CY7C1415KV18 000 Description Version number.
11010011011000111 11010011011001111 11010011011010111 11010011011100111 Defines the type of SRAM. 00000110100 00000110100 00000110100 00000110100 Allows unique identification of SRAM vendor. Indicates the presence of an ID register.
1
1
1
1
Scan Register Sizes
Register Name Instruction Bypass ID Boundary scan Bit Size 3 1 32 109
Instruction Codes
Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures the input and output ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the input and output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a high Z state. Do Not Use: This instruction is reserved for future use. Captures the input and output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
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Boundary Scan Order
Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Bump ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H Bit # 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Bump ID 10G 9G 11F 11G 9F 10F 11E 10E 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B Bit # 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 Bump ID 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D 3C 1D 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H Bit # 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Bump ID 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R Internal
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Power Up Sequence in QDR II SRAM
QDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
PLL Constraints

PLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var. The PLL functions at frequencies down to 120 MHz. If the input clock is unstable and the PLL is enabled, then the PLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 20 s of stable clock to relock to the desired clock frequency.
Power Up Sequence
Apply power and drive DOFF either HIGH or LOW (All other inputs can be HIGH or LOW). Apply VDD before VDDQ. Apply VDDQ before VREF or at the same time as VREF. Drive DOFF HIGH. Provide stable DOFF (HIGH), power and clock (K, K) for 20 s to lock the PLL.
Figure 3. Power Up Waveforms
K K
~ ~
Unstable Clock
> 20 s Stable clock
~ ~
Start Normal Operation
Clock Start (Clock Starts after V DD / V DDQ Stable)
VDD / VDDQ
DOFF
V DD / V DDQ Stable (< +/- 0.1V DC per 50ns ) Fix HIGH (or tie to VDDQ)
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ -65 C to +150 C Ambient temperature with power applied . -55 C to +125 C Supply voltage on VDD relative to GND ........-0.5 V to +2.9 V Supply voltage on VDDQ relative to GND....... -0.5 V to +VDD DC applied to outputs in high Z ........ -0.5 V to VDDQ + 0.3 V DC input voltage[20] ............................. -0.5 V to VDD + 0.3 V Current into outputs (LOW) ......................................... 20 mA Static discharge voltage (MIL-STD-883, M. 3015).. > 2001 V Latch-up current .................................................... > 200 mA
* No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to Application Note AN 54908 "Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates"
Neutron Soft Error Immunity
Parameter LSBU LMBU SEL Description Logical single-bit upsets Logical multi-bit upsets Single event latch-up Test Conditions 25 C 25 C 85 C Typ 197 0 0 Max* 216 0.01 0.1 Unit FIT/ Mb FIT/ Mb FIT/ Dev
Operating Range
Range Commercial Industrial Ambient Temperature (TA) 0 C to +70 C -40 C to +85 C VDD[21] 1.8 0.1 V VDDQ[21] 1.4 V to VDD
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range[22] Parameter VDD VDDQ VOH VOL VOH(LOW) VOL(LOW) VIH VIL IX IOZ VREF Description Power supply voltage I/O supply voltage Output HIGH voltage Output LOW voltage Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input leakage current Output leakage current Input reference voltage[25] GND VI VDDQ GND VI VDDQ, Output Disabled Typical Value = 0.75V Note 23 Note 24 IOH =0.1 mA, Nominal Impedance IOL = 0.1 mA, Nominal Impedance Test Conditions Min 1.7 1.4 VDDQ/2 - 0.12 VDDQ/2 - 0.12 VDDQ - 0.2 VSS VREF + 0.1 -0.3 5 5 0.68 Typ 1.8 1.5 - - - - - - - - 0.75 Max 1.9 VDD VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2 VDDQ + 0.3 VREF - 0.1 5 5 0.95 Unit V V V V V V V V A A V
Notes 20. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5 V (Pulse width less than tCYC/2). 21. Power-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 22. All voltage referenced to Ground. 23. Output are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175 ohms RQ 350 ohms. 24. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 ohms RQ 350 ohms. 25. VREF (min) = 0.68 V or 0.46 VDDQ, whichever is larger, VREF (max) = 0.95 V or 0.54 VDDQ, whichever is smaller.
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Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range[22] Parameter IDD
[26]
(continued)
Description VDD operating supply
Test Conditions VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC 333 MHz (x 8) (x 9) (x 18) (x 36) 300 MHz (x 8) (x 9) (x 18) (x 36) 250 MHz (x 8) (x 9) (x 18) (x 36) 200 MHz (x 8) (x 9) (x 18) (x 36) 167 MHz (x 8) (x 9) (x 18) (x 36)
Min - - - - - - - - - - - - - - - - - - - -
Typ - - - - - - - - - - - - - - - - - - - -
Max 560 560 570 790 520 520 540 730 460 460 470 640 400 400 410 540 360 360 370 480
Unit mA
mA
mA
mA
mA
Note 26. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-57826 Rev. *B
Page 23 of 33
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Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range[22] Parameter ISB1 Description Automatic power-down current Test Conditions Max VDD, both ports deselected, VIN VIH or VIN VIL f = fMAX = 1/tCYC, inputs static 333 MHz (x 8) (x 9) (x 18) (x 36) 300 MHz (x 8) (x 9) (x 18) (x 36) 250 MHz (x 8) (x 9) (x 18) (x 36) 200 MHz (x 8) (x 9) (x 18) (x 36) 167 MHz (x 8) (x 9) (x 18) (x 36) Min - - - - - - - - - - - - - - - - - - - - Typ - - - - - - - - - - - - - - - - - - - - Max 280 280 280 280 270 270 270 270 260 260 260 260 250 250 250 250 250 250 250 250 mA mA mA mA Unit mA
(continued)
AC Electrical Characteristics
Over the Operating Range[16] Parameter VIH VIL Description Input HIGH voltage Input LOW voltage Test Conditions Min VREF + 0.2 - Typ - - Max - VREF - 0.2 Unit V V
Document Number: 001-57826 Rev. *B
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Capacitance
Tested initially and after any design or process change that may affect these parameters. Parameter CIN CO Description Input capacitance Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V Max 4 4 Unit pF pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters. Parameter JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 165 FBGA Package 13.7 3.73 Unit C/W C/W
Figure 4. AC Test Loads and Waveforms
VREF = 0.75 V VREF OUTPUT Device Under Test Z0 = 50 RL = 50 0.75 V VREF OUTPUT 5 pF 0.25 V Slew Rate = 2 V/ns 0.75 V R = 50 ALL INPUT PULSES 1.25 V 0.75 V
[27]
ZQ
(a)
Device Under VREF = 0.75 V Test ZQ
RQ = 250
INCLUDING JIG AND SCOPE
RQ = 250 (b)
Note 27. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 4.
Document Number: 001-57826 Rev. *B
Page 25 of 33
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Switching Characteristics
Over the Operating Range[28, 29] Cypress Consortium Parameter Parameter tPOWER tCYC tKH tKL tKHKH tKHCH tKHKH tKHKL tKLKH tKHKH tKHCH Description VDD(typical) to the first access[30] K clock and C clock cycle time Input clock (K/K; C/C) HIGH Input clock (K/K; C/C) LOW 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Unit ms ns ns ns ns ns
Min Max Min Max Min Max Min Max Min Max 1 3.0 1.20 1.20 - 8.4 - - - 1.30 1 3.3 1.32 1.32 1.49 0 - 8.4 - - - 1.45 1 4.0 1.6 1.6 1.8 0 - 8.4 - - - 1.8 1 5.0 2.0 2.0 2.2 0 - 8.4 - - - 2.2 1 6.0 2.4 2.4 2.7 0 - 8.4 - - - 2.7
K clock rise to K clock rise and C to 1.35 C rise (rising edge to rising edge) K/K clock rise to C/C clock rise (rising edge to rising edge) 0
Setup Times tSA tSC tSCDDR tAVKH tIVKH tIVKH Address set-up to K clock rise Control set-up to K clock rise (RPS, WPS) Double data rate control setup to clock (K/K) rise (BWS0, BWS1, BWS2, BWS3) D[X:0] set-up to clock (K/K) rise Address hold after K clock rise Control hold after K clock rise (RPS, WPS) Double data rate control hold after clock (K/K) rise (BWS0, BWS1, BWS2, BWS3) D[X:0] hold after clock (K/K) rise 0.4 0.4 0.3 - - - 0.4 0.4 0.3 - - - 0.5 0.5 0.35 - - - 0.6 0.6 0.4 - - - 0.7 0.7 0.5 - - - ns ns ns
tSD tHA tHC tHCDDR
tDVKH tKHAX tKHIX tKHIX
0.3
-
0.3
-
0.35
-
0.4
-
0.5
-
ns
Hold Times 0.4 0.4 0.3 - - - 0.4 0.4 0.3 - - - 0.5 0.5 0.35 - - - 0.6 0.6 0.4 - - - 0.7 0.7 0.5 - - - ns ns ns
tHD
tKHDX
0.3
-
0.3
-
0.35
-
0.4
-
0.5
-
ns
Notes 28. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 4 on page 25. 29. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is operated and outputs data with the output timings of that frequency range. 30. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before a read or write operation is initiated.
Document Number: 001-57826 Rev. *B
Page 26 of 33
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Switching Characteristics
Cypress Consortium Parameter Parameter Output Times tCO tDOH tCCQO tCQOH tCQD tCQDOH tCQH tCQHCQH tCHZ tCLZ tKC Var tKC lock tKC Reset tCHQV tCHQX tCHCQV tCHCQX tCQHQV tCQHQX tCQHCQL tCQHCQH tCHQZ tCHQX1 tKC Var tKC lock tKC Reset C/C clock rise (or K/K in single clock mode) to data valid Data output hold after output C/C clock rise (active to active) C/C clock rise to echo clock valid - -0.45 - 0.45 - 0.45 - 0.25 -0.25 1.25 1.25 - -0.45 - - - 0.45 - -0.27 1.4 1.4 - -0.45 - -0.45 - -0.45 0.45 - 0.45 - 0.27 - - - 0.45 - -0.30 1.75 1.75 - -0.45 - -0.45 - -0.45 0.45 - 0.45 - 0.30 - - - 0.45 - -0.35 2.25 2.25 - -0.45 - -0.45 - -0.45 0.45 - 0.45 - 0.35 - - - 0.45 - -0.40 2.75 2.75 - -0.50 - -0.50 - -0.50 0.50 - 0.50 - 0.40 - - - 0.50 - ns ns ns ns ns ns ns ns ns ns
Over the Operating Range[28, 29]
(continued) 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz
Description
Min Max Min Max Min Max Min Max Min Max
Unit
Echo clock hold after C/C clock rise -0.45 Echo clock high to data valid Echo clock high to data invalid Output clock (CQ/CQ) HIGH[31] CQ clock rise to CQ clock rise (rising edge to rising edge)[31] Clock (C/C) rise to high Z (active to high Z)[32, 33] Clock (C/C) rise to low Z [32, 33]
PLL Timing Clock phase jitter PLL lock time (K, C) K static to PLL reset
[34]
- 20 30
0.20 - -
- 20 30
0.20 - -
- 20 30
0.20 - -
- 20 30
0.20 - -
- 20 30
0.20 - -
ns s ns
Notes 31. These parameters are extrapolated from the input timing parameters (tCYC/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by design and are not tested in production 32. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of Figure 4 on page 25. Transition is measured 100 mV from steady-state voltage. 33. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO. 34. For frequencies 300 MHz or below, the Cypress QDR II devices surpass the QDR consortium specification for PLL lock time (tKC lock) of 20 s (min. spec.) and will lock after 1024 clock cycles (min. spec.), after a stable clock is presented, per the previous 90 nm version.
Document Number: 001-57826 Rev. *B
Page 27 of 33
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Switching Waveforms
Figure 5. Read/Write/Deselect Sequence[35, 36, 37]
NOP 1
K
t KH tKL
READ 2
t CYC
WRITE 3
t KHKH
READ 4
WRITE 5
NOP 6
7
K RPS
t SC
tHC
t SC
t HC
WPS A
A0 tSA t HA t SD D10 D11 A1 A2 t HD t SD D12 D13 D30 D31 D32 D33 A3 t HD
D Q
t KHCH t KHCH t CLZ
Q00
Q01 tCO
Q02
Q03
Q20
Q21
Q22
Q23
tCQDOH t CQD
t CHZ
t DOH
C
t CYC t KHKH t KH t KL
C
t CQOH t CCQO
CQ
t CQH
t CQHCQH
t CQOH
t CCQO
CQ DON'T CARE UNDEFINED
Notes 35. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1. 36. Outputs are disabled (high Z) one clock cycle after a NOP. 37. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 001-57826 Rev. *B
Page 28 of 33
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Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (MHz) 333 Ordering Code CY7C1426KV18-333BZC CY7C1413KV18-333BZC CY7C1415KV18-333BZC CY7C1415KV18-333BZXC CY7C1413KV18-333BZI 300 CY7C1426KV18-300BZC CY7C1413KV18-300BZC CY7C1426KV18-300BZXC CY7C1413KV18-300BZXC CY7C1415KV18-300BZXC CY7C1415KV18-300BZI CY7C1415KV18-300BZXI 250 CY7C1426KV18-250BZC CY7C1413KV18-250BZC CY7C1415KV18-250BZC CY7C1426KV18-250BZXC CY7C1413KV18-250BZXC CY7C1415KV18-250BZXC CY7C1413KV18-250BZI CY7C1415KV18-250BZI CY7C1413KV18-250BZXI CY7C1415KV18-250BZXI 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-free 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial Industrial 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial Commercial Package Diagram Package Type Operating Range Commercial
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Ordering Code Definitions
CY 7C 14XX K V18 - XXX BZ X C Temperature Range: C = Commercial = 0 C to +70 C X = Pb-free; X Absent = Leaded Package Type: BZ = 165-ball FPBGA Speed Grade: XXX = 333 MHz / 300 MHz / 250 MHz V18 = 1.8 V VDD Process Technology 65 nm 14XX = 1413 or 1415 or 1426 = Part Identifier Marketing Code: 7C = SRAMs Company ID: CY = Cypress
Document Number: 001-57826 Rev. *B
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Package Diagram
Figure 6. 165-ball FBGA (13 x 15 x 1.4 mm), 51-85180
51-85180 *C
Document Number: 001-57826 Rev. *B
Page 30 of 33
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Acronyms
Acronym DDR FBGA HSTL I/O JTAG LSB MSB PLL QDR SRAM TAP TCK TMS TDI TDO TQFP double data rate fine-pitch ball grid array high-speed transceiver logic input/output joint test action group least significant bit most significant bit phase locked loop quad data rate static random access memory test access port test clock test mode select test data-in test data-out thin quad flat pack % s ms ns V A mA mm MHz pF W C Description
Document Conventions
Units of Measure
Symbol ohms percent micro seconds milli seconds nano seconds Volts micro Amperes milli Amperes milli meter Mega Hertz pico Farad Watts degree Celcius Unit of Measure
Document Number: 001-57826 Rev. *B
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Document History Page
Document Title: CY7C1411KV18/CY7C1426KV18/CY7C1413KV18/CY7C1415KV18, 36-Mbit QDR(R) II SRAM 4-Word Burst Architecture Document Number: 001-57826 Rev. ** *A ECN No. 3018546 Orig. of Change NJY Submission Description of change Date 11/27/2009 10/21/2010 New Data Sheet Converted from Preliminary to Final. Added Ordering Code Definitions. Updated Package Diagram. Minor edits and updated in new template. Added Note 34. Updated Ordering Information. Added Acronyms and Units of Measure.
2816620 VKN/AESA
*B
3165654
NJY
02/08/2011
Document Number: 001-57826 Rev. *B
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.
Products
Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
(c) Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-57826 Rev. *B
Revised March 1, 2011
Page 33 of 33
QDR II is a registrered trademark of Cypress Semiconductor Corporation. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders.
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